The present invention relates to the field of integrated circuits; more specifically, it relates to reducing soft errors in integrated circuits that include dynamic circuits. BACKGROUND OF THE INVENTION Dynamic circuits, such as domino circuits, for example, are widely used in high-speed integrated circuit designs. This is because dynamic circuits typically provide area and speed advantages over corresponding static complementary metal oxide semiconductor (CMOS) circuits.
Dynamic circuits, however, are more vulnerable to soft errors as compared to their static counterparts. A soft error is a transient, single event upset that changes the state of a circuit node or other internal storage element. Soft errors, for example, may be caused by alpha particles or cosmic rays impinging on the integrated circuit device.
Alpha particles are charged particles that may originate from the decay of trace impurities in integrated circuit packaging materials, for example. Cosmic rays may include heavy ions and protons that, either directly or indirectly, may have an ionization effect within the integrated circuit device semiconductor material. In either case, the charged particles from these sources may change the charge at an integrated circuit node such that the node actually transitions to an opposite logical state.
The critical charge (Qcrit) at a node is an indication of the susceptibility of the node to such soft errors. Qcrit is the minimum charge beyond which operation of a circuit will be affected. Thus, if an ion strike causes charge collected at a node to exceed Qcrit, the node may erroneously transition from a logical one state to a logical zero state, or from a logical 0 to a logical 1 state.
Since the maximum frequency at which an integrated circuit can be clocked depends on the Qcrit of the circuit, the immunity of the circuit must be traded off against the clock frequency. Clock frequency is adversely effected by higher Qcrit levels in dynamic circuits. The same integrated circuit may be used in multiple applications. High performance applications require high clock frequencies and thus a lower Qcrit. High reliability applications require high Qcrit, but must run at lower clock frequencies. A given device may be used in either application. A single device may be used in a high reliability mode at one moment and in a high performance mode another moment.
Therefore, the tradeoff between reliability against soft errors expressed as a Qcrit level and performance of a dynamic circuits presents designers of dynamic circuits significant problems.
A first aspect of the present invention is an integrated circuit comprising: a dynamic logic gate having an output node at which a logical output value of the logic gate is detected; and selectable circuit means for alteration of the soft error susceptibility of the dynamic logic gate.
A second aspect of the present invention is an integrated circuit comprising: a dynamic logic gate having an output node at which a logical output value of the logic gate is detected; and a keeper circuit adapted to selectively alter the critical charge of the dynamic logic gate.
A third aspect of the present invention is an integrated circuit comprising: a dynamic logic gate having an output node at which a logical output value of the logic gate is detected; a keeper circuit providing a level of critical charge to the output node; and a body bias circuit, the body bias circuit adapted to selectively alter the bias voltage applied to the bodies of input devices of the dynamic logic gate.